It is well known to provide extra columns in a DRAM device so that in the event of failure of a memory cell in a column, that column can be deleted from operation and in effect replaced by an operative (redundant) column.
One approach for implementing such a system is what is called "shift redundancy", which is described in the IEEE Journal of Solid-State Circuits Article, Volume 26, No. 4, April 1991, entitled "A 7-ns 1Mb BiCMOS ECL SRAM with Shift Redundancy", by Ohba et al. Reference is made to FIG. 1 herein for a description of a typical circuit embodying shift redundancy. In that circuit, data is obtained from each memory cell in a column through a bit line pair (B0 B0, B1 B1, B2 B2, B3 B3, B4 B4, B5 B5). This data passes through respective sense amplifiers 20, 22, 24, 26, 28, 30 and multiplexers 32, 34, 36, 38, 40, 42 to data output lines D0-D5. Further included is a redundant column pair containing bit line BRED BRED. With each of the bit line pairs BO BO-B5 B5 operating, all fuses F1-F7 in line 14 are intact (unblown), so that VCC applied to both the fuse F7 and the fuse F1 insures that low signals are applied by inverters 46-56 to the control terminals of the multiplexers 32-42. This provides the appropriate signal from the bit line pair to the data output line of the associated multiplexer. That is, bit line pair B0 B0 provides a signal on data output line D0, bit line pair B1 B1 provides a signal on date output line D1 and so forth.
In the event that, for example, the column including bit line pair B2 B2 is defective, and it is desired to bring in BRED and BRED, fuse F3 is blown, as is fuse F7, tying the line 44 rightward of fuse F3 to ground. The inverters 50-56 associated with multiplexers 36, 38, 40, 42 then provide a high signal at the control terminals of those multiplexers 36-42, so that the input signal provided to terminal B of each of the multiplexers 36-42 is provided at the data output line of that multiplexer. Thus, the column containing bit line pair B2 B2 is excluded, while the data associated with bit line pair B3 B3 is provided to multiplexer 36 and to data output D2. Likewise, the data associated with bit line pair B4 B4 is applied to multiplexer 38 and data output line D3, and so forth, bringing BRED BRED into the array.
While such a system has in the past been relatively effective in use, as dimensions of parts become internally smaller, it is becoming more common that a defect falls on adjacent columns, i.e., rendering at least two adjacent columns inoperative. It will be seen that the above-described system is not capable of dealing with such a problem.
Another type of system for replacing a defective column in a memory device is decode redundancy. An example of such a system is shown in FIG. 2. Redundant bit lines B, B are shown therein. Assuming, for example, that the address line A5 A6 A7 . A8 previously addressed a defective memory cell in a column, and that defective column is then excluded by blowing an appropriate fuse, it is now desirable to incorporate the bit line pair B B in its place, to be addressed by that address line, A5 A6 A7 . A8. In that case, fuse 70 would be blown, so that the transistor pair 72 is no longer tied to ground. Furthermore, fuses 74, 76, 78 would be blown. In addition, fuses 80, 82, 84 of stage 99 would be blown (fuse 86 being left intact), while fuses 88, 90 would be blown (leaving fuses 92, 94 intact). This connects up the input line A5 A6 A7 . A8 through the stage 99 to the bit line pair B B.
While this system allows replacement of any defective column anywhere in a memory array, a main disadvantage is that a very large number of fuses must be blown, and a price is paid in speed performance.